Coding process for a signal processor, and processor for the implementation of such a process

ABSTRACT

A special purpose processor for data processing. A transformation is determined in order to represent the input and output data as multidimensional spaces. The transformation is represented by an input matrix and an output matrix. These matrices make it possible to program the selection of the input and output data in a systematic manner and to determine a processor structure which is especially adapted to such programming. The system simplifies the use of processors operating in parallel.

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION

The present invention relates to processes which make it possible tocode special-purpose signal processors. It relates also to signalprocessors allowing the implementation of such a process.

DISCUSSION OF THE BACKGROUND

It is known that apart from processors of a general type such as thoseused for example in personal computers, there are special-purposeprocessors, especially those intended for processing signals whosestructure is especially adapted to the simultaneous execution of severalactivities. The activities are systematic and involve access to thememories, calculations on data and management of the number ofiterations.

By way of example of such a processor mention will be made of thosemanufactured by the company Analog Device under the references 21020 or21060.

By referring to the technical handsheet for such a processor, it may beobserved that the processing of the data is carried out essentially byrepeating two types of elementary actions. One of these actions consistsin successively obtaining a certain number of addresses in the memory byusing a data address generator (DAG). The other of these actionsconsists in performing a particular processing operation on the datathus selected and in iterating this processing operation a specifiednumber of times with the aid of a repetition counter (loop count stack).The generating of the addresses and the management of the length of theloop are determined by programming. The programming of these two actionsis done separately and the relations between the two are determined bythe human programmer, who devises the programs by making a mental noteof the necessary relations. There is therefore no automatic aspect and arisk of errors exists.

The inventor has already developed a signal processing applicationgraphical input process making it possible to formalize the signalprocessing applied to such signals by presenting them in the form ofinput and output arrays and by establishing systematic relations betweenthese arrays.

This formalism leads to the development of a special-purpose signalprocessor enabling it to be implemented directly. This graphical inputprocess has formed the subject of a French Patent Application filed bythe Applicant on Apr. 7, 1995 under No. 95 04175.

The formalism in question has also formed the subject of a paper at the1995 GRETSI colloquium at JUAN LES PINS, FRANCE.

Finally, it is planned to present this formalism, as well as programmingtools, on the Internet from the University of Berkeley server at theaddress:

http://ptolemy.eecs.berkeley.edu.

This formalism, which can also be regarded as a language, is known inthe art by the name ARRAY-OL.

In the framework of these studies, the inventors have also invented acoding process making it possible to unify the two repetitive actionsdescribed above, so as automatically to have the desired result withoutbeing obliged to link the two operations mentally at programming level.

SUMMARY OF THE INVENTION

To do this, the invention proposes a coding process for a signalprocessor, which starts from an input array which is sampled with aninput pattern according to an input assembling relation and an inputpaving relation, each of these patterns is subjected to an elementarytransformation TE which delivers output patterns, and an output array isconstructed by assembling these output patterns according to an outputpaving relation and an output fitting relation, principallycharacterized in that a first output multidimensional space isdetermined, comprising a first set of axes corresponding to the axes ofthe quotient array resulting from dividing the output array by theoutput pattern itself regarded as an output divisor array, and a secondset of axes corresponding to the axes of this output divisor array, thisfirst space thus comprising all the outputs of the output array arrangedin such a way as to be able to be traversed successively by anincrementation of the clock of the processor, and in that a firstprojection matrix from this first space to the output array isdetermined, this making it possible automatically to determine a firstcoding for placing the outputs in the output array.

According to another characteristic, a second input multidimensionalspace is determined, comprising a third set of axes corresponding to theaxes of the quotient array resulting from dividing the input array bythe input pattern itself regarded as an input divisor array, the axes ofthis third set being identical to those of the first, and a fourth setof axes corresponding to the axes of this input divisor array, thissecond space thus comprising all the inputs of the input array arrangedin such a way as to be able to be traversed successively by anincrementation of the clock of the processor, and in that a secondprojection matrix from the input array to the second space isdetermined, this making it possible moreover automatically to determinea second coding for selecting the inputs in the input array.

The invention also proposes a processor for implementing the process,principally characterized in that it comprises a first counter intendedto be incremented by a clock and comprising as many stages as axes inthe first and the second set of axes, the number of states which eachstage can take being equal to the dimension of the first space on theaxis corresponding to this stage, in that it comprises a first and asecond set of multipliers intended to multiply the outputs of the stagesby the coefficients of the said first matrix, and in that it comprises afirst and a second summator for respectively adding up the outputs ofthe adders of the first and second sets of multipliers and fordelivering the coefficients of the vector which makes it possible toplace the outputs in the output array.

According to another characteristic, the processor furthermore comprisesa second counter intended to be incremented by the said clock andcomprising as many stages as axes in the fourth set of axes, the numberof states which each stage can take being equal to the dimension of thesecond space on the axis corresponding to this stage, in that itcomprises a third and a fourth set of multipliers intended to multiplythe outputs of the stages of this second counter and the outputs of thestages of the first counter corresponding to the axes common to thefirst and to the second spaces by the coefficients of the said secondmatrix, and in that it comprises a third and a fourth summator forrespectively adding up the outputs of the adders of the third and fourthsets of multipliers and for delivering the coefficients of the vectorwhich makes it possible to select the inputs in the input array.

According to another characteristic, each multiplier consists of anaccumulator operating at the rate of the signals of the clock, theoutput of which is looped onto the input by way of an adder whichreceives the value of the necessary multiplier coefficient, and whosereset-to-zero input is linked to the output of the corresponding stage.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention will emerge clearly fromthe following description presented by way of non-limiting example inconjunction with the appended figures which represent:

FIG. 1, an elementary graphic for defining the concepts and vocabularyused in the description of the invention;

FIG. 2, an example of an array of results;

FIG. 3, the "quotient" array obtained by dividing the array of FIG. 2 bythe pattern;

FIG. 4, a representation of the array of FIG. 2 in a Cartesian space of4 dimensions;

FIG. 5, an example of the implementation of the operations making itpossible to go from the array of FIG. 4 to that of FIG. 2;

FIG. 6, a simplification of the multiplier stages of FIG. 5;

FIG. 7, an example of an elementary transformation TE showing that theinput and output patterns are generated differently;

FIG. 8, a representation in a Cartesian space of 4 dimensions of aninput array;

FIG. 9, a simplified input array with the first three patterns arisingfrom the paving; and

FIG. 10, an example of a complete implementation of the input and outputoperations.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Represented in FIG. 1 is a set of data 101 placed in an equidistantmanner on an axis 102 and corresponding to an input E. These data arefor example successive samples over time originating from a singlehydrophone.

The processing of these data is done in successive iterations, eachcorresponding for example to an incrementation over time.

At each iteration, a group of data is selected, defined by a so-called"fitting" relation. In this example, the fitting relation consists inselecting one datum out of two.

The group of data thus selected, four in this example, therefore forms a"pattern" which is subjected to elementary transformation TE symbolizedby a large arrowhead 103. In this example, this elementarytransformation can for example be a weighted addition which gives asingle result 104.

At the next increment, the group of data forming the next pattern isselected based on displacing the previous group by a so-called "paving"distance, which here is 9 spacings. Of course, the fitting for obtainingthis pattern is the same as the previous one. The fitting correspondingto the first operation is represented by solid lines between the dataselected the first time. The fitting corresponding to the data selectedat the next increment with the paving relation is represented by dashedlines.

The results 104 are then grouped together in this example on an axis 105to form the output information S. The placing of these results 104 onthe axis 105 to form the succession of output data 106 is done solelywith the aid of a paving relation since here the output pattern ispoint-like. In this example, for simplicity of explanation, this issimply a trailing of the results 104 one after the other, since theyform a single datum.

Here again the line which joins the result 104 to the output datum 106is solid for the first operation and dashed for the second.

The iteration is then continued, still using the paving relation.

These definitions are generalized in the case in which the data, moregenerally the inputs, originate from several sources and so havepreferably to be placed, for the understanding and arrangement of theprocessing operations, in representations manifesting several dimensionsor several sources. Pursuing the above example, the successive samplesover time originating from a set of aligned hydrophones forming forexample a sonar antenna will be placed in a rectangular array. Toprocess these signals they will be grouped together with the aid of apattern subjected to fitting and paving relations. After applying a TEto the successive patterns, the results of these processing operationswill be placed back in a results array.

Represented in FIG. 2 is such a results array in which the outputs 201are distributed according to a Cartesian coordinate layout having twoaxes A0 and A1. The description starts from the results array so as toshow that the invention makes it possible to obtain, from a simpletransformation on this array, a matrix which makes it possible to unifythe abovementioned operations. It will then be shown that using the sametransformation it is possible, knowing the two input and output patternsof the transformation TE, to unify the same operations on the input dataarray. However, the results pattern can be one-dimensional.

Thus, although in an input array there is in the general case no reasonwhy the successive patterns selected from this array by the paving so asto be presented to the TE operation should be abutting so as to form acontinuous paving, the opposite is the case in a results array where allthe results have to be calculated, once only. Hence, a priori theyexhibit no redundancy nor require any separating.

The array of FIG. 2 is in this example formed of 15 columns of 8 resultsgrouped into 20 identical contiguous patterns 202 each comprising 3columns of 2 results. To simplify the figure, the noughts 201 depictingthese results are represented in only one of the patterns.

Hence, since the patterns are identical the array can then be simplifiedby restricting it to one point per pattern, given that this pointrepresents the six results of the relevant pattern. The array of FIG. 3is then obtained, comprising 5 columns and 4 rows of points representedby small squares 301. Since this array is the result of dividing that ofFIG. 2 by the pattern, it is termed the quotient array, with dimensions0/3 and 0/4 on axes Q1 and Q0. As a clear reminder that a pointcorresponds to a pattern, the pattern 312 associated with the extremepoint 302 has been represented superimposed and skewed. This pattern isthen termed the divisor array of the result array, with dimensions 0/1and 0/2 on axes D0 and D1.

A last simplification then consists in representing the result array inthe form of a parallelepiped in a Cartesian space of four dimensions asin FIG. 4. This space comprises four axes:

two axes Q1=A1/D1 and Q0=A0/D0;

two axesD1 and D0; and the parallelepiped therefore has 4 dimensions ofrespective sizes 4, 5, 2 and 3.

Any result from the array therefore corresponds to a point with integercoordinates of this parallelepiped, which may be represented by a vector{r}={q1, q0, d1, d0}.

Likewise, this result in the array A1/A0 is a two-dimensional vector{R}={a1, a0}.

The correspondence between these two vectors can be obtained by aprojection matrix such that: {R}={MP}×{r}.

In this example, the matrix in question, where the first two columnscorrespond to the paving relation, and the last two to the fittingrelation, is given by: ##EQU1##

The benefit of this representation is that it is possible to deducetherefrom a hardware implementation which indeed makes it possible toobtain the abovestated unification of the two actions.

In an example of an embodiment of such an implementation, represented inFIG. 5, a counter formed of four stages 501 to 504 is employed. Thesestages can take 3, 2, 5 and 4 states respectively.

A clock at the input of stage 501 increments the latter, and when thelatter returns to zero it increments the stage 502, and so on untilstage 504 returns to zero, thereby delivering an end-of-operationsignal.

Hence, for each clock stroke the state of the set of stages of thecounter gives the value of one of the vectors {r} contained in theparallelepiped of the space of FIG. 4.

Hence, at the end of the operations the entire array of results has beentraversed, this array being expressed in the form Q/D of FIG. 4.

To obtain these results in the form of the array of FIG. 2, which allows"natural" exploitation of these results, the vector thus obtained mustbe multiplied by the matrix {MP}.

To do this, at each clock stroke the content of the stages of thecounter are multiplied by the values of the coefficients of the matrix.

To do this, use is made of four multipliers 511 to 514 into which arefed the coefficients 0, 1, 0 and 2, and four multipliers 521 to 524 intowhich are fed the coefficients 1, 0, 3 and 0. Of course, the value 0makes it possible to dispense with a multiplier, but the latter can beused for other versions of the circuit which are programmed differently.

By then adding up the results of the multiplications in summators 505(for 511 to 514) and 506 (for 521 to 524), the coefficients a1 and a0 ofthe vector {R} are obtained, giving the position of the result in theresult array of FIG. 2.

Since the multipliers are expensive components, a cheaper solution,represented in FIG. 6, consists for each stage such as 601 in linkingits input to the clock input H of an accumulator 602 whose output islooped back to its own input by way of an adder 603 which also receivesthe value of the multiplier coefficient N. This output is applied alsoto the corresponding summator.

The output of stage 601 is applied to the reset-to-zero input of theaccumulator, and when this stage returns to zero so does theaccumulator.

The same reasoning makes it possible to represent the input array as aCartesian space of four dimensions. This space will be different fromthat described earlier since the TE operation generally maps inputpatterns and results of different dimensions. For example, asrepresented in FIG. 7, the pattern 202 of FIG. 2 is obtained by a TEoperation 701, of filtering for example, on a pattern 702 comprising 2columns and 5 rows.

However, since the TE delivers a single pattern of results from a singlepattern of inputs, it is clear that in the Cartesian space of theinputs, the axes Q1 and Q0 will be the same. The other two axes,corresponding to the divisor pattern, will be different and will betermed D'1 and D'0.

Hence, given the size of the pattern, the parallelepiped which in thisCartesian space represents the input array will have dimensions 3, 4, 4and 1, as represented in FIG. 8. The axes Q1 and Q0 will then be definedby the relations:

Q1=A'1/D'1 and Q0=A'0/D'0 in which the axes A'1 and A'0 are now the axesof the input array.

Every input of the array therefore corresponds to a point with integercoordinates of this parallelepiped, which can be represented by a vector{e}={q1, q0, d'1, d'0}.

Likewise, this input in the "natural" array A'1/A'0 is a two-dimensionalvector {E}={a'1, a'0}.

Here again the mapping between these two vectors can be obtained byanother projection matrix such that: {E}={MP'}×{e}.

This matrix is of course to be defined as a function of the fitting andpaving relations applied to the array A'1/A'0. We have seen that theserelations might be much more complex than in the array A1/A0.

By way of example, represented in a partial manner in FIG. 9 is an inputarray comprising a base pattern 901 and the first two following patternstaken on the axes Q1 and Q0. The inputs defining the ends of the unitvectors on the axes Q1 and Q0 have been denoted by crosses. It may beobserved that all the elements thus represented are sufficient to definethe transformation, and hence the matrix, for going from {E} to {e}.

In this example, the matrix in question, where the first two columnscorrespond to the paving relation, and the last two to the fittingrelation, is given by: ##EQU2##

It is observed that on account of the skewed shifting of the patterns inthe paving relation, and correspondingly of the axes Q1 and Q0, there isno zero in the first two columns of the matrix.

Hence, in the same way as for the array of results, it is possible toobtain a hardware implementation which here again enables the twoactions to be unified as stated earlier. Furthermore, thisimplementation can contain a part which is common with that used for theresults array since the calculation of the coefficients ql and qO is thesame.

The diagram represented in a very simplified manner in FIG. 10 is thenobtained, where the rectangles 1001 to 1004 make it possible to obtaindO, d1, q0 and q1 and supply the rectangle 1005 to obtain a1 and a0.

It is then sufficient to insert the components 1011 and 1012 to obtaind'0 and d'1 and supply the component 1015, which, also being supplied bythe components 1003 and 1004, delivers a'1 and a'0.

It is therefore observed that this single autonomously operatingassembly makes it possible to obtain the read loops (1011, 1012), thewrite loops (1001-1002), the iteration loops for the TE (1003, 1004) andthe assembly of components 1001 to 1004 and 1011 and 1012 may be viewedas a repetition counter.

These diagrams are merely schematic diagrams and in a concreteembodiment the person skilled in the art would for example use a RAMmemory, registers, adders and comparators, thereby enabling theinvention to be extended to any number of dimensions and to any size ineach dimension.

What is claimed is:
 1. A coding process for a signal processor forautomatically determining a first coding for storage addresses for aplurality of outputs in an output array, said signal processor includinga clock, the coding process comprising the steps of:determining a firstoutput multidimensional space, including a first set of axes and asecond set of axes; inputting an input array including a first pluralityof input data elements; selecting a second plurality of data elementsfrom said first plurality of data elements by using an input patternaccording to a first input relation and a second input relation;transforming said input pattern according to an elementarytransformation to generate an output pattern of output data elements;generating said output array by ordering a plurality of said outputpattern of said output data elements based on a first output relationand a second output relation, wherein said first set of axes correspondto axes of a quotient array generated by dividing said output array bysaid output pattern, said second set of axes correspond to axes of saidoutput pattern, and said first output multidimensional space includesall output data elements of said output array ordered for successivetraversal according to a first incrementation of said clock; anddetermining a first projection matrix from said first outputmultidimensional space to said output array.
 2. The coding processaccording to claim 1, wherein:said first input relation indicates afirst ordered selection of input based on a predetermined number of saidfirst plurality of input data elements for generating a first group ofsaid input data elements, and said second input relation indicates asecond ordered selection of input from said first group.
 3. The codingprocess according to claim 1, further comprising the stepsof:determining a second input multidimensional space, including a thirdset of axes and a fourth set of axes, whereinsaid third set of axescorrespond to axes of a quotient array generated by dividing said inputarray by said input pattern, wherein said third set of axes is identicalto said first set of axes, and wherein said fourth set of axescorrespond to axes of said input pattern, and said second inputmultidimensional space includes all input data elements of said inputarray ordered for successive traversal according to a secondincrementation of said clock; and determining a second projection matrixfrom said input array to said second input multidimensional space,wherein said coding process automatically determines a second coding forselecting inputs in said input array.
 4. A processor for implementing acoding process for automatically determining a first coding for storageaddresses for a plurality of outputs in an output array, said processorcomprising:a clock; a first counter, including a first set ofmultipliers, a second set of multipliers, a first summator, and a secondsummator; a device configured to determine a first outputmultidimensional space, including a first set of axes and a second setof axes; a device configured to input an input array including a firstplurality of input data elements; a device configured to select a secondplurality of data elements from said first plurality of data elements byusing an input pattern according to a first input relation and a secondinput relation; a device configured to transform said input patternaccording to an elementary transformation to generate an output patternof output data elements; a device configured to generate said outputarray by ordering a plurality of said output pattern of said output dataelements based on a first output relation and a second output relation,whereinsaid first set of axes correspond to axes of a quotient arraygenerated by dividing said output array by said output pattern, saidsecond set of axes correspond to axes of said output pattern, and saidfirst output multidimensional space includes all output data elements ofsaid output array ordered for successive traversal according to a firstincrementation of said clock; and a device configured to determine afirst projection matrix from said first output multidimensional space tosaid output array, whereinsaid first counter is incremented by saidclock, and said first counter includes a number of first stages which isat least as large as a number of axes included in said first and secondsets of axes, wherein each one of said first stages includes a number offirst states which is equal to a dimension of a first space of one ofsaid axes included in said first and second sets of axes whichcorresponds to said each one of said first stages, and wherein saidfirst and second sets of multipliers multiply outputs of said firststages of said first counter by a plurality of coefficients of saidfirst projection matrix, and each one of said first set of multipliersincludes at least one first adder and each one of said second set ofmultipliers includes at least one second adder, said first summator addsoutputs of said at least one first adder and said second summator addsoutputs of said at least one second adder to generate coefficients of anoutput vector for placing outputs in said output array.
 5. The processoraccording to claim 4, wherein:said first input relation indicates afirst ordered selection of input based on a predetermined number of saidfirst plurality of input data elements for generating a first group ofsaid input data elements, and said second input relation indicates asecond ordered selection of input from said first group.
 6. Theprocessor according to claim 4, further comprising:a device configuredto determine a second input multidimensional space, including a thirdset of axes and a fourth set of axes, whereinsaid third set of axescorrespond to axes of a quotient array generated by dividing said inputarray by said input pattern, wherein said third set of axes is identicalto said first set of axes, and wherein said fourth set of axescorrespond to axes of said input pattern, and said second inputmultidimensional space includes all input data elements of said inputarray ordered for successive traversal according to a secondincrementation of said clock; and a device configured to determine asecond projection matrix from said input array to said second inputmultidimensional space, wherein said coding process automaticallydetermines a second coding for selecting inputs in said input array. 7.The processor according to claim 4, further comprising:a second counter,including a third set of multipliers, a fourth set of multipliers, athird summator, and a fourth summator; a device configured to determinea second input multidimensional space, including a third set of axes anda fourth set of axes, whereinsaid third set of axes correspond to axesof a quotient array generated by dividing said input array by said inputpattern, wherein said third set of axes is identical to said first setof axes, and wherein said fourth set of axes correspond to axes of saidinput pattern, and said second input multidimensional space includes allinput data elements of said input array ordered for successive traversalaccording to a second incrementation of said clock; and a deviceconfigured to determine a second projection matrix from said input arrayto said second input multidimensional space, wherein said coding processautomatically determines a second coding for selecting inputs in saidinput array, whereinsaid second counter is incremented by said clock,and said second counter includes a number of second stages which is atleast as large as a number of axes included in said fourth set of axes,wherein each one of said second stages includes a number of secondstates which is equal to a dimension of a second space of one of saidaxes included in said fourth set of axes which corresponds to said eachone of said second stages, and wherein said third and fourth sets ofmultipliers multiply outputs of said second stages of said secondcounter and outputs of said first stages of said first countercorresponding to axes common to said first output multidimensional spaceand said second input multidimensional space by a plurality ofcoefficients of said second projection matrix, and each one of saidthird set of multipliers includes at least one third adder and each oneof said fourth set of multipliers includes at least one fourth adder,said third summator adds outputs of said at least one third adder andsaid fourth summator adds outputs of said at least one fourth adder togenerate coefficients of an input vector for selecting inputs in saidinput array.
 8. The processor according to claim 7, wherein eachmultiplier of said first and second sets of multipliers comprises anaccumulator operating at the rate of the signals of said clock, whereinan output of said accumulator is looped onto an input of saidaccumulator by an accumulator adder, wherein said accumulator adderreceives the value of a multiplier coefficient, and wherein areset-to-zero input of said accumulator adder is linked to an output ofa corresponding first stage of said first counter.